PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 44

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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3.2 FUNCTIONAL OVERVIEW
The KBC supports two external devices — a keyboard and
a mouse. Each device communicates with the KBC via two
bidirectional serial signals. Five additional external general-
purpose I/O signals are provided.
KBC operation involves three signal interfaces:
These system interfaces are shown in Figure 3-2.
The KBC uses two data registers (for input and output) and
a status register to communicate with the part central sys-
tem. Data exchange between these units may be based on
programmed I/O or interrupt-driven.
The KBC has two internal interrupts: the Input Buffer Full
(IBF) interrupt and Timer Overflow interrupt (see Figure
3-1). These two interrupts can be independently enabled or
disabled by KBC firmware. Both are disabled by a hard re-
set. These two interrupts only affect the execution flow of
the KBC firmware, and have no connection with the external
interrupts requested by this logical device.
The KBC can generate two external interrupt requests.
These request signals are controlled by the KBC firmware
which generates them by manipulating I/O port signals. See
Section 3.3.2.
The part supports the KBC and handles interactions with
the PC chip set. In addition to data transfer, these interac-
tions include KBC configuration, activation and status mon-
itoring. The part interconnects with the host via one
interface that is shared by all chip devices
•
•
•
External I/O interface
Internal KBC - PC87307/PC97307 interface
PC87307/PC97307 - PC chip set interface.
Chipset
PC
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
SA15-0
XD7-0
IRQn
AEN
RD
MR
D7-0
WR
A15-0
Plug and
FIGURE 3-2. System Interfaces
Matrix
Play
Mouse IRQ
KBC IRQ
PC87307/PC97307
44
The KBC clock is generated from the main clock of the chip,
which may come from an external clock source or from the
internal frequency multiplier. (See Sections 3.3 and 3-4.)
The KBC clock rate is configured by the SuperI/O (SIO)
Configuration Registers.
3.3 DEVICE CONFIGURATION
The KBC hardware contains two logical devices—the KBC
(logical device 0) and the mouse (logical device 1).
3.3.1
The KBC has two I/O addresses and one IRQ line (KBC
IRQ) and can operate without the companion mouse.
The mouse cannot operate without the KBC device. It has
one IRQ line (mouse IRQ) but has no I/O address. It utilizes
the KBC I/O addresses.
3.3.2
The KBC IRQ and Mouse IRQ interrupt request signals are
identical to (or functions of) the P24 and P25 signals of the
8042. These interrupt request signals are routed internally
to the Plug and Play interrupt Matrix and may be routed to
user-programmable IRQ pins. Each logical device is inde-
pendently controlled.
The Interrupt Select registers (index 70h for each logical de-
vice) select the IRQ pin to which the corresponding interrupt
request is routed. The interrupt may also be disabled by not
routing its request signal to any IRQ pin.
Bit 0 of the Interrupt Type registers (index 71h for each log-
ical device) determines whether the interrupts are passed
(bit 0 = 0) or latched (bit 0 = 1). If bit 0 = 0, interrupt request
signals (P24 and P25) are passed directly to the selected
IRQ pin. If bit 0 = 1, interrupt request signals that become
active are latched on their rising edge, and held until read
from the KBC output buffer (port 60h).
Figure 3-3 illustrates the internal interrupt request logic.
DBBOUT
STATUS
DBBIN
P24
P25
I/O Address Space
Interrupt Request Signals
TEST0
KBC
TEST1
P26
P27
P10
P23
P22
P11
P12
P16
P17
P20
P21
KBCLK
Keyboard Clock
KBDAT
Keyboard Data
MCLK
Mouse Clock
MDAT
Mouse Data