PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 116

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
6.3.4
This control port is read or write. A write operation to it sets
the state of four pins on the 25-pin D-shell connector, and
controls both the parallel port interrupt enable and direction.
The bits of this register have the identical function in EPP
modes as in SPP modes. See Section 6.2.4 for a detailed
description of each bit.
6.3.5
This port is added in EPP modes to enhance system
throughput by enabling registers in the remote device to be
directly addressed by hardware.
This port can be read or written. Writing to it initiates an EPP
device or register selection operation.
1
0
7
7
FIGURE 6-6. SPP or EPP CTR Register Bitmap
Reserved
A7
1
0
6
6
FIGURE 6-7. EPP ADDR Register Bitmap
SPP or EPP Control Register (CTR), Offset 02h
EPP Address Register (ADDR), Offset 03h
A6
Reserved
0
0
5
5
Direction Control
A5
0
0
4
4
A4
Interrupt Enable
0
0
3
3
A3
Parallel Port Input Control
0
0
2
2
EPP Device or
Register Selection
Address Bits
A2
Printer Initialization Control
0
0
1
1
Automatic Line Feed Control
A1
0
0
0
0
Reset
Required
Reset
Required
A0
Data Strobe Control
SPP or EPP Control
Register (ADDR)
Register (CTR)
EPP Address
Parallel Port (Logical Device 4)
Offset 02h
Offset 03h
116
6.3.6
DATA0 is a read/write register. Accessing it initiates device
read or write operations of bits 7 through 0.
6.3.7
DATA1 is only accessed to transfer bits 15 through 8 of a
16/32-bit read or write to EPP Data Register 0 (DATA0).
6.3.8
This is the third EPP data register. It is only accessed to
transfer bits 23 through 16 of a 32-bit read or write to EPP
Data Register 0 (DATA0).
0
0
0
7
7
7
D7
D15
D23
0
0
0
6
6
6
FIGURE 6-10. EPP DATA2 Register Bitmap
FIGURE 6-8. EPP DATA0 Register Bitmap
FIGURE 6-9. EPP DATA1 Register Bitmap
EPP Data Register 0 (DATA0), Offset 04h
EPP Data Register 1 (DATA1), Offset 05h
EPP Data Register 2 (DATA2), Offset 06h
D6
D14
D22
0
0
0
5
5
5
D5
D13
D21
0
0
0
4
4
4
D4
D12
D20
0
0
0
3
3
3
D3
D11
D19
0
0
0
2
2
2
EPP Device
Read or Write Data
EPP Device
Read or Write Data
D2
D10
D18
EPP Device
Read or Write Data
0
0
0
1
1
1
D1
D17
0
0
0
0
0
0
D9
D0
D16
Reset
Required
Reset
Required
Reset
Required
D8
EPP Data Register 0
EPP Data Register 1
EPP Data Register 2
Offset 04h
Offset 05h
Offset 06h
(DATA0)
(DATA1)
(DATA2)