PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 142

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
Interrupt Enable Register (IER), in the Non-Extended
Modes (UART, SIR and Sharp-IR)
Upon reset, the IER supports UART, SIR and Sharp-IR in
the Non-Extended modes. Figure 7-5 shows the bitmap of
the Interrupt Enable Register in these modes.
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
Bit 2 - Link Status Interrupt Enable (LS_IE)
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Bits 7-4 - Reserved
0
7
FIGURE 7-5. IER Register Bitmap, Non-Extended
Setting this bit enables interrupts on Receiver High-
Data-Level, or RX_FIFO Time-Out events (EIR Bits 3-0
are 0100 or 1100. See “Non-Extended Mode Interrupt
Priorities” on page 144).
0 - Disable Receiver High-Data-Level and RX_FIFO
1 - Enable Receiver High-Data-Level and RX_FIFO
Setting this bit enables interrupts on Transmitter Low
Data-Level-events (EIR Bits 3-0 are 0010. See “Non-
Extended Mode Interrupt Priorities” on page 144).
0 - Disable Transmitter Low-Data-Level Interrupts (De-
1 - Enable Transmitter Low-Data-Level Interrupts.
Setting this bit enables interrupts on Link Status events.
(EIR Bits 3-0 are 0110. See “Non-Extended Mode Inter-
rupt Priorities” on page 144).
0 - Disable Link Status Interrupts (LS_EV) (Default).
1 - Enable Link Status Interrupts (LS_EV).
Setting this bit enables the interrupts on Modem Status
events. (EIR Bits 3-0 are 0000. See See Table 7-3 on
page 144).
0 - Disable Modem Status Interrupts (MS_EV) (De-
1 - Enable Modem Status Interrupts (MS_EV).
These bits are reserved.
Reserved
0
6
Time-Out interrupts (Default).
Time-Out interrupts.
fault).
fault).
Reserved
0
5
Reserved
0
4
IER in Non-Extended Modes
Reserved
0
3
0
MS_IE
2
LS_IE
0
1
Mode
TXLDL_IE
0
0
RXHDL_IE
Reset
Required
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
Interrupt Enable
Register (IER)
Offset 01h
Bank 0,
142
Interrupt Enable Register (IER), in the Extended Modes
of UART, Sharp-IR and SIR
Figure 7-6 shows the bitmap of the Interrupt Enable Regis-
ter in these modes.
FIGURE 7-6. IER Register Bitmap, Extended Modes of
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
Bit 2 - Link Status Interrupt Enable (LS_IE)
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Bit 4 - DMA Interrupt Enable (DMA_IE)
0
7
Setting this bit enables interrupts when the RX_FIFO is
equal to or above the RX_FIFO threshold level, or an
RX_FIFO time out occurs.
0 - Disable Receiver Data Ready interrupt. (Default)
1 - Enable Receiver Data Ready interrupt.
Setting this bit enables interrupts when the TX_FIFO is
below the threshold level or the Transmitter Holding
Register is empty.
0 - Disable Transmitter Low-Data-Level Interrupts (De-
1 - Enable Transmitter Low-Data-Level Interrupts.
Setting this bit enables interrupts on Link Status events.
0 - Disable Link Status Interrupts (LS_EV) (Default)
1 - Enable Link Status Interrupts (LS_EV).
Setting this bit enables the interrupts on Modem Status
events.
0 - Disable Modem Status Interrupts (MS_EV) (De-
1 - Enable Modem Status Interrupts (MS_EV).
Setting this bit enables the interrupt on terminal count
when the DMA is enabled.
0 - Disable DMA terminal count interrupt (Default)
1 - Enable DMA terminal count interrupt.
Reserved
Extended Mode of UART, Sharp-IR and SIR
0
6
fault).
fault)
Reserved
0
5
0
TXEMP_IE
4
DMA_IE
0
3
UART and Sharp-IR
0
MS_IE
2
LS_IE
0
1
TXLDL_IE
0
0
RXHDL_IE
Reset
Required
Interrupt Enable
Register (IER)
Offset 01h
Bank 0,