PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 191

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

16.3
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
The SPBRGH:SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
Table 16-3 contains the formulas for determining the
baud rate. Example 16-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 16-5. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRG register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
TABLE 16-3:
TABLE 16-4:
© 2009 Microchip Technology Inc.
Legend:
TXSTA
RCSTA
BAUDCON ABDOVF
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Name
SYNC
0
0
0
0
1
1
EUSART Baud Rate Generator
(BRG)
x = Don’t care, n = value of SPBRGH, SPBRG register pair
Configuration Bits
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
CSRC
SPEN
Bit 7
BAUD RATE FORMULAS
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
BRG16
0
0
1
1
0
1
RCIDL
Bit 6
RX9
TX9
BRGH
0
1
0
1
x
x
DTRXP
SREN
TXEN
Bit 5
PIC18F1XK50/PIC18LF1XK50
CKTXP
SYNC
CREN
Bit 4
Preliminary
BRG/EUSART Mode
16-bit/Asynchronous
16-bit/Asynchronous
16-bit/Synchronous
8-bit/Asynchronous
8-bit/Asynchronous
8-bit/Synchronous
ADDEN
SENDB
BRG16
Bit 3
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 16-1:
Calculated Baud Rate
For a device with F
of 9600, Asynchronous mode, 8-bit BRG:
Solving for SPBRGH:SPBRG:
Desired Baud Rate
BRGH
FERR
Bit 2
—
Error
X =
OERR
TRMT
WUE
Bit 1
OSC
=
=
=
=
=
=
=
(
CALCULATING BAUD
RATE ERROR
(
Calc. Baud Rate Desired Baud Rate
------------------------------------------------------------------------------------------- -
-------------------------------------------------------------------- -
64 [SPBRGH:SPBRG]
[
9615
(
----------------------------------
-------------------------- -
64 25
64 * (Desired Baud Rate)
16000000
25.042
9615 9600
of 16 MHz, desired baud rate
16,000,000
64 * 9600
(
(
Baud Rate Formula
9600
–
ABDEN
+
F
F
F
TX9D
RX9D
]
Desired Baud Rate
Bit 0
OSC
OSC
1
OSC
=
)
F
F
25
/[64 (n+1)]
/[16 (n+1)]
OS C
OSC
/[4 (n+1)]
)
DS41350C-page 189
=
–
0.16%
Reset Values
)
-1
on page
+
281
281
281
281
281
1
)
)
-1