PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 209
PIC18F13K50-E/P
Manufacturer Part Number
PIC18F13K50-E/P
Description
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F13K50-EP.pdf
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17.1.6
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
Conversion. The ADC interrupt flag is the ADIF bit in
the PIR1 register. The ADC interrupt enable is the ADIE
bit in the PIE1 register. The ADIF bit must be cleared by
software.
TABLE 17-1:
17.1.7
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON2 register controls the output format.
Figure 17-2 shows the two output formats.
FIGURE 17-2:
© 2009 Microchip Technology Inc.
Legend: Shaded cells are outside of recommended range.
Note 1:
ADC Clock Source
Note:
F
F
F
2:
3:
4:
(ADFM = 0)
(ADFM = 1)
F
F
F
OSC
OSC
OSC
OSC
OSC
OSC
F
ADC Clock Period (T
RC
The F
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the F
conversion will be performed during Sleep.
INTERRUPTS
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
RESULT FORMATTING
/16
/32
/64
/2
/4
/8
RC
ADC CLOCK PERIOD (T
source has a typical T
10-BIT A/D CONVERSION RESULT FORMAT
MSB
bit 7
bit 7
Unimplemented: Read as ‘0’
ADCS<2:0>
AD
000
100
001
101
010
110
x11
)
ADRESH
PIC18F1XK50/PIC18LF1XK50
AD
10-bit A/D Result
time of 1.7 μs.
AD
41.67 ns
83.33 ns
) V
1-4 μs
167 ns
333 ns
667 ns
48 MHz
1.33 μs
Preliminary
S
. DEVICE OPERATING FREQUENCIES
MSB
(1,4)
AD
(2)
(2)
(2)
(2)
(2)
time.
bit 0
bit 0
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine. Please see Section 17.1.6
“Interrupts” for more information.
1-4 μs
RC
125 ns
250 ns
500 ns
Device Frequency (F
16 MHz
1.0 μs
2.0 μs
4.0 μs
clock source is only recommended if the
bit 7
bit 7
(1,4)
(2)
(2)
(2)
10-bit A/D Result
LSB
Unimplemented: Read as ‘0’
1-4 μs
16.0 μs
500 ns
8.0 μs
4 MHz
1.0 μs
2.0 μs
4.0 μs
ADRESL
OSC
(1,4)
(3)
(2)
(3)
)
DS41350C-page 207
1-4 μs
16.0 μs
32.0 μs
64.0 μs
8.0 μs
1 MHz
2.0 μs
4.0 μs
bit 0
LSB
bit 0
(1,4)
(3)
(3)
(3)
(3)
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