PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 222

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PIC18F13K50-E/P

Manufacturer Part Number
PIC18F13K50-E/P
Description
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
PIC18F1XK50/PIC18LF1XK50
DS41350C-page 220
FIGURE 18-2:
V
C1RSEL
FVR
REF
C12IN1-
C12IN2-
C12IN3-
C1IN+
C1CH<1:0>
AGND
0
1
MUX
C1V
C1R
COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
REF
0
1
2
3
0
1
2
MUX
MUX
Note 1:
2:
3:
4:
C1V
C1V
C1SP
When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
Positive going pulse generated on both falling and rising edges of the bit.
IN
IN
-
+
+
-
From TMR1L[0]
C1
C1ON
C1POL
(1)
Preliminary
Q3*RD_CM1CON0
(4)
Q1
D
NReset
Q
D
EN
C1OUT
C1SYNC
Q
D
EN
0
1
CL
Q
© 2009 Microchip Technology Inc.
RD_CM1CON0
OSC
To PWM Logic
).
SYNCC1OUT
Data Bus
Set C1IF
C2OE
C1OE
C12OUT
To

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