PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 25

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

2.13.3
The Fail-Safe condition is cleared by either one of the
following:
• Any Reset
• By toggling the SCS1 bit of the OSCCON register
Both of these conditions restart the OST. While the
OST is running, the device continues to operate from
the INTOSC selected in OSCCON. When the OST
times out, the Fail-Safe condition is cleared and the
device automatically switches over to the external clock
source. The Fail-Safe condition need not be cleared
before the OSCFIF flag is cleared.
2.13.4
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
FIGURE 2-7:
TABLE 2-6:
© 2009 Microchip Technology Inc.
CONFIG1H
INTCON
OSCCON
OSCTUNE
PIE2
PIR2
T1CON
Legend:
Note 1:
Clock Monitor Output
Name
Sample Clock
Note:
RESET OR WAKE-UP FROM SLEEP
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
FAIL-SAFE CONDITION CLEARING
OSCFIF
System
GIE/GIEH PEIE/GIEL
Output
INTSRC
OSCFIE
OSCFIF
Clock
IDLEN
RD16
IESO
Bit 7
(Q)
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
FSCM TIMING DIAGRAM
SPLLEN
FCMEN
T1RUN
IRCF2
Bit 6
C1IE
C1IF
T1CKPS1
PCLKEN
TMR0IE
IRCF1
Test
TUN5
Bit 5
C2IE
C2IF
PIC18F1XK50/PIC18LF1XK50
Preliminary
T1CKPS0 T1OSCEN T1SYNC
PLLEN
INT0IE
IRCF0
TUN4
EEIE
EEIF
Bit 4
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
FOSC3
RABIE
BCLIE
BCLIF
OSTS
TUN3
Bit 3
Note:
Test
Oscillator
Failure
TMR0IF
HFIOFS
FOSC2
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock
completed.
USBIE
USBIF
TUN2
Bit 2
switchover
TMR1CS TMR1ON
TMR3IE
TMR3IF
FOSC1
INT0IF
SCS1
TUN1
Bit 1
Detected
Failure
FOSC0
RABIF
SCS0
TUN0
has
Bit 0
Test
—
—
DS41350C-page 23
successfully
Values on
Reset
page
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