PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 299

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

24.2.1
Register 24-15 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
REGISTER 24-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER
TABLE 24-2:
24.3
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into five blocks.
One of these is a boot block of 0.5K or 2K bytes,
depending on the device. The remainder of the mem-
ory is divided into individual blocks on binary boundar-
ies.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
RCON
WDTCON
CONFIG2H
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
®
Name
microcontroller devices.
U-0
—
Program Verification and
Code Protection
CONTROL REGISTER
Unimplemented: Read as ‘0’
SWDTEN: Software Enable or Disable the Watchdog Timer bit
1 = WDT is turned on
0 = WDT is turned off (Reset value)
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
—
U-0
—
SBOREN
Bit 6
—
W = Writable bit
‘1’ = Bit is set
U-0
—
Bit 5
PIC18F1XK50/PIC18LF1XK50
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0
U-0
Preliminary
—
Bit 4
RI
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Figure 24-2 shows the program memory organization
for 8, 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
Bit 3
U-0
TO
—
—
Bit 2
PD
—
(1)
U-0
—
Bit 1
POR
—
x = Bit is unknown
U-0
—
SWDTEN
WDTEN
Bit 0
BOR
DS41350C-page 297
SWDTEN
R/W-0
on page
Values
Reset
272
280
290
bit 0
(1)