PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 40

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
TABLE 3-2:
DS41350C-page 38
TMR0H
TMR0L
T0CON
OSCCON
OSCCON2
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
REFCON2
REFCON1
REFCON0
PSTRCON
BAUDCON
PWM1CON
ECCP1AS
TMR3H
TMR3L
T3CON
Legend:
Note
File Name
1:
2:
3:
Timer0 Register, High Byte
Timer0 Register, Low Byte
Timer1 Register, High Byte
Timer1 Register, Low Bytes
Timer2 Register
Timer2 Period Register
SSP Receive Buffer/Transmit Register
SSP Address Register in I
A/D Result Register, High Byte
A/D Result Register, Low Byte
Capture/Compare/PWM Register 1, High Byte
Capture/Compare/PWM Register 1, Low Byte
Timer3 Register, High Byte
Timer3 Register, Low Byte
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
Bits RA0 and RA1 are available only when USB is disabled.
ECCPASE
TMR0ON
ABDOVF
FVR1EN
PRSEN
IDLEN
WCOL
GCEN
ADFM
RD16
P1M1
D1EN
RD16
Bit 7
IPEN
SMP
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F1XK50/PIC18LF1XK50) (CONTINUED)
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1
ECCPAS2
ACKSTAT
FVR1ST
T08BIT
T1RUN
SSPOV
D1LPS
RCIDL
IRCF2
PDC6
P1M0
Bit 6
CKE
—
—
—
—
—
—
—
—
(1)
2
C™ Slave Mode. SSP Baud Rate Reload Register in I
ECCPAS1
T3CKPS1
T1CKPS1
DAC1OE
FVR1S1
SSPEN
ACKDT
ACQT2
DC1B1
DTRXP
IRCF1
T0CS
CHS3
PDC5
Bit 5
D/A
—
—
—
—
—
—
STRSYNC
ECCPAS0
T1CKPS0
T3CKPS0
DAC1R4
FVR1S0
ACKEN
ACQT1
CKTXP
DC1B0
IRCF0
CHS2
PDC4
T0SE
Bit 4
CKP
—
—
RI
—
---
P
Preliminary
T2OUTPS0
T1OSCEN
PVCFG1
CCP1M3
DAC1R3
D1PSS1
PSSAC1
T3CCP1
SSPM3
ACQT0
BRG16
RCEN
OSTS
CHS1
TSEN
STRD
PDC3
Bit 3
PSA
TO
—
—
S
TMR2ON
PVCFG0
CCP1M2
T1SYNC
DAC1R2
D1PSS0
PSSAC0
T3SYNC
PRI_SD
SSPM2
ADCS2
T0PS2
STRC
CHS0
TSRS
PDC2
IOSF
Bit 2
PEN
R/W
PD
—
—
2
C Master Mode.
GO/DONE
T2CKPS1
TMR1CS
TMR3CS
NVCFG1
CCP1M1
DAC1R1
PSSBD1
HFIOFL
SSPM1
ADCS1
T0PS1
RSEN
STRB
PDC1
SCS1
WUE
Bit 1
POR
UA
—
—
—
© 2009 Microchip Technology Inc.
T2CKPS0
SWDTEN
TMR1ON
TMR3ON
NVCFG0
CCP1M0
DAC1R0
PSSBD0
LFIOFS
SSPM0
ABDEN
ADCS0
D1NSS
T0PS0
ADON
STRA
PDC0
SCS0
Bit 0
BOR
SEN
BF
—
0000 0000 280, 99
xxxx xxxx 280, 99
1111 1111 280, 97
0011 qq00 280, 16
---- -10x 280, 17
0q-1 11q0
xxxx xxxx 280, 106
xxxx xxxx 280, 106
0000 0000 280, 101
0000 0000 280, 108
1111 1111 280, 108
-000 0000 280, 107
xxxx xxxx
0000 0000 280, 144
0000 0000
0000 0000
0000 0000 280, 147
xxxx xxxx 281, 217
xxxx xxxx 281, 217
--00 0000 281, 211
---- 0000 281, 212
0-00 0000 281, 213
xxxx xxxx 281, 133
xxxx xxxx 281, 133
0000 0000 281, 113
---0 0000 281, 244
000- 00-0 281, 243
0001 00-- 281, 243
---0 0001 281, 129
0100 0-00 281, 188
0000 0000 281, 128
0000 0000 281, 125
xxxx xxxx 281, 111
xxxx xxxx 281, 111
0-00 0000 281, 109
POR, BOR
--- ---0 280, 297
Value on
143, 144
137, 146
137, 146
Details
278, 74
page:
271,
280,
280,
280,
on