PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 263
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PIC18F13K50-E/P
Manufacturer Part Number
PIC18F13K50-E/P
Description
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F13K50-EP.pdf
(414 pages)
- Current page: 263 of 414
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22.5.1.1
The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend or while the
USB module is suspended. A few clock cycles are
required to synchronize the internal hardware state
machine before the ACTVIF bit can be cleared by
firmware. Clearing the ACTVIF bit before the internal
hardware is synchronized may not have an effect on
the value of ACTVIF. Additionally, if the USB module
uses the clock from the 48 MHz PLL source, then after
EXAMPLE 22-1:
© 200C Microchip Technology Inc.
Assembly:
LOOP:
DONE:
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }
BCF
BTFSS
BRA
BCF
BRA
Bus Activity Detect Interrupt Bit
(ACTVIF)
UCON, SUSPND
UIR, ACTVIF
DONE
UIR, ACTVIF
LOOP
CLEARING ACTVIF BIT (UIR<2>)
PIC18F1XK50/PIC18LF1XK50
Preliminary
clearing the SUSPND bit, the USB module may not be
immediately operational while waiting for the 48 MHz
PLL to lock. The application code should clear the
ACTVIF flag as shown in Example 22-1.
Only one ACTVIF interrupt is generated when resum-
ing from the USB bus Idle condition. If user firmware
clears the ACTVIF bit, the bit will not immediately
become set again, even when there is continuous bus
traffic. Bus traffic must cease long enough to generate
another IDLEIF condition before another ACTVIF
interrupt can be generated.
DS41350C-page 261
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