PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 250

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
REGISTER 22-2:
DS41350C-page 248
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
UTEYE
R/W-0
The UPUEN, and FSEN bits should never be changed while the USB module is enabled. These values
must be preconfigured prior to enabling the module.
UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test enabled
0 = Eye pattern test disabled
Unimplemented: Read as ‘0’
UPUEN: USB On-Chip Pull-up Enable bit
1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up disabled
Unimplemented: Read as ‘0’
FSEN: Full-Speed Enable bit
1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
PPB<1:0>: Ping-Pong Buffers Configuration bits
11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers enabled for all endpoints
01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers disabled
U-0
—
UCFG: USB CONFIGURATION REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
(1)
UPUEN
R/W-0
Preliminary
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
FSEN
R/W-0
(1)
© 200C Microchip Technology Inc.
x = Bit is unknown
R/W-0
PPB1
R/W-0
PPB0
bit 0