PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 240

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
TABLE 20-1:
REGISTER 20-2:
DS41350C-page 238
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
SRCLK
SRLEN
R/W-0
111
110
101
100
011
010
001
000
Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.
SRLEN: SR Latch Enable bit
1 = SR latch is enabled
0 = SR latch is disabled
SRCLK<2:0>
000 = 1/4 Peripheral cycle clock
001 = 1/8 Peripheral cycle clock
010 = 1/16 Peripheral cycle clock
011 = 1/32 Peripheral cycle clock
100 = 1/64 Peripheral cycle clock
101 = 1/128 Peripheral cycle clock
110 = 1/256 Peripheral cycle clock
111 = 1/512 Peripheral cycle clock
SRQEN: SR Latch Q Output Enable bit
If SRNQEN = 0
1 = Q is present on the RC4 pin
0 = Q is internal only
SRNQEN: SR Latch Q Output Enable bit
1 = Q is present on the RC4 pin
0 = Q is internal only
SRPS: Pulse Set Input of the SR Latch
1 = Pulse input
0 = Always reads back ‘0’
SRPR: Pulse Reset Input of the SR Latch
1 = Pulse input
0 = Always reads back ‘0’
Divider
SRCLK FREQUENCY TABLE
512
256
128
SRCLK2
64
32
16
8
4
R/W-0
SRCON0: SR LATCH CONTROL REGISTER
F
(1)
OSC
W = Writable bit
‘1’ = Bit is set
: SR Latch Clock divider bits
SRCLK1
25.6 μs
12.8 μs
6.4 μs
3.2 μs
1.6 μs
0.8 μs
0.4 μs
0.2 μs
R/W-0
= 20 MHz
(1)
SRCLK0
F
R/W-0
OSC
Preliminary
0.25 μs
0.5 μs
32 μs
16 μs
8 μs
4 μs
2 μs
1 μs
= 16 MHz
U = Unimplemented
‘0’ = Bit is cleared
SRQEN
R/W-0
F
OSC
0.5 μs
64 μs
32 μs
16 μs
8 μs
4 μs
2 μs
1 μs
= 8 MHz F
SRNQEN
R/W-0
OSC
128 μs
© 2009 Microchip Technology Inc.
64 μs
32 μs
16 μs
8 μs
4 μs
2 μs
1 μs
= 4 MHz
C = Clearable only bit
x = Bit is unknown
R/W-0
SRPS
F
OSC
512 μs
256 μs
128 μs
64 μs
32 μs
16 μs
8 μs
4 μs
R/W-0
SRPR
= 1 MHz
bit 0