MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 121

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

7.4.2.2 Computer Operating Properly (COP) Reset
7.4.2.3 Illegal Opcode Reset
7.4.2.4 Illegal Address Reset
68HC908AZ32A — Rev 0.0
MOTOROLA
CGMXCLK
CGMOUT
PORRST
OSC1
RST
IAB
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
CONFIG-1 register is at logic zero.
See
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the CONFIG-1 register is logic zero, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset.
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register SRSR) and
CYCLES
Freescale Semiconductor, Inc.
4096
Section 13. Computer Operating Properly
For More Information On This Product,
Figure 7-7. POR Recovery
System Integration Module (SIM)
CYCLES
Go to: www.freescale.com
32
CYCLES
32
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System Integration Module (SIM)
Reset and System Initialization
(COP).
Advance Information
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