MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 294

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Timer Interface Module A (TIMA)
18.8 I/O Signals
18.8.1 TIMA Clock Pin (PTD6/ATD14/
TACLK)
18.8.2 TIMA Channel I/O Pins (PTF3/TCH5–PTF0/TCH2 and PTE3/TCH1–PTE2/TCH0)
Advance Information
294
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
Port D shares one of its pins with the TIMA. Port E shares two of its pins
with the TIMA and port F shares four of its pins with the TIMA.
PTD6/ATD14/TCLK is an external clock input to the TIMA prescaler. The
six TIMA channel I/O pins are PTE2/TCH0, PTE3/TCH1, PTF0/TCH2,
PTF1/TCH3, PTF2/TCH4, and PTF3/TCH5.
PTD6/ATD14/TCLK is an external clock input that can be the clock
source for the TIMA counter instead of the prescaled internal bus clock.
Select the PTD6/ATD14/TCLK input by writing logic 1s to the three
prescaler select bits, PS[2:0] (see
Register). The minimum TCLK pulse width, TCLK
The maximum TCLK frequency is the least: 4 MHz or bus frequency 2.
PTD6/ATD14/TCLK is available as a general-purpose I/O pin or ADC
channel when not used as the TIMA clock input. When the
PTD6/ATD14/TCLK pin is the TIMA clock input, it is an input regardless
of the state of the DDRD6 bit in data direction register D.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE2/TCH0, PTF0/TACH2 and
Freescale Semiconductor, Inc.
For More Information On This Product,
Timer Interface Module A (TIMA)
Go to: www.freescale.com
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bus frequency
1
18.9.1 TIMA Status and Control
+
t
SU
68HC908AZ32A — Rev 0.0
LMIN
or TCLK
MOTOROLA
HMIN
, is: