MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 264

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Serial Peripheral Interface (SPI)
17.9 Queuing Transmission Data
Advance Information
264
Two sources in the SPI status and control register can generate CPU
interrupt requests:
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates
when the transmit data buffer is ready to accept new data. Write to the
SPI data register only when the SPTE bit is high.
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA:CPOL = 1:0).
1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every
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time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
Serial Peripheral Interface (SPI)
Figure 17-8. SPI Interrupt Request Generation
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SPRIE
SPTE
SPTIE
SPRF
SPE
68HC908AZ32A — Rev 0.0
Figure 17-9
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
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