MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 383

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

23.8.2 Data Direction Register F
68HC908AZ32A — Rev 0.0
MOTOROLA
NOTE:
NOTE:
Address:
TBCH[1:0] — Timer B Channel I/O Bits
Data direction register F (DDRF) does not affect the data direction of port
F pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic 1 to a DDRF bit enables the output buffer for
the corresponding port F pin; a logic 0 disables the output buffer.
DDRF[6:0] — Data Direction Register F Bits
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 23-19
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
The PTF5/TBCH1–PTF4 pins are the TIMB input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTF5/TBCH1–PTF4 pins are timer channel I/O pins or
general-purpose I/O pins. (See
on page 324).
These read/write bits control port F data direction. Reset clears
DDRF[6:0], configuring all port F pins as inputs.
For More Information On This Product,
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
$000D
Bit 7
Figure 23-18. Data Direction Register F (DDRF)
R
R
0
0
Go to: www.freescale.com
shows the port F I/O logic.
= Reserved
DDRF6
6
0
I/O Ports
Table
DDRF5
5
0
23-6).
DDRF4
4
0
TIMB Status and Control Register
DDRF3
3
0
DDRF2
2
0
Advance Information
DDRF1
1
0
I/O Ports
DDRF0
Bit 0
Port F
0
383