MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 267

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

17.11.2 Stop Mode
17.12 SPI During Break Interrupts
68HC908AZ32A — Rev 0.0
MOTOROLA
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). (See
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after the MCU exits stop mode. If stop mode is exited by reset,
any transfer in progress is aborted and the SPI is reset.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR, $FE03) enables software to
clear status bits during the break state. (See
Register
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the data register in break mode will not initiate a
transmission nor will this data be transferred into the shift register.
Freescale Semiconductor, Inc.
For More Information On This Product,
on page 134).
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
Interrupts
on page 263).
Serial Peripheral Interface (SPI)
SIM Break Flag Control
SPI During Break Interrupts
Advance Information
267