HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 191

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HD6412320

Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Bit 3
MXC1
0
1
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the
number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This
setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled.
Bit 1
RLW1
0
1
Bit 2
MXC0
0
1
0
1
Bit 0
RLW0
0
1
0
1
Description
8-bit shift
9-bit shift
10-bit shift
Description
No wait state inserted
1 wait state inserted
2 wait states inserted
3 wait states inserted
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
Rev.6.00 Sep. 27, 2007 Page 161 of 1268
Section 6 Bus Controller
REJ09B0220-0600
23
23
23
23
23
23
(Initial value)
(Initial value)
to A
to A
to A
to A
to A
to A
8
9
10
9
10
11
used
used
used
used
used
used

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