HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 236

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
Usage Notes: When DRAM space * is accessed, the ICIS0 and ICIS1 bit settings are disabled. In
the case of consecutive reads between different areas, for example, if the second access is a
DRAM access * , only a T
cycle is inserted, and a T
cycle is not. The timing in this case is shown
p
I
in figure 6.34.
However, in burst access in RAS down mode these settings are enabled, and an idle cycle is
inserted. The timing in this case is shown in figures 6.35 (a) and (b).
Note: * The DRAM interface is not supported in the H8S/2321.
External read
DRAM space read
T
T
T
T
T
T
T
1
2
3
p
r
c1
c2
φ
Address bus
RD
Data bus
Figure 6.34 Example of DRAM Access after External Read
Rev.6.00 Sep. 27, 2007 Page 206 of 1268
REJ09B0220-0600