HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 910

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 ROM
Rev.6.00 Sep. 27, 2007 Page 880 of 1268
REJ09B0220-0600
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first
Note 7: Write Pulse Width
Note: Use a (z3) µs write pulse for additional
5. A write pulse of (z1) or (z2) μs should be applied according to the progress
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.2.6, Flash Memory Characteristics.
2. Verify data is read in 16-bit (W) units.
3. Even bits for which programming has been completed in the 128-byte
4. A 128-byte area for storing program data, a 128-byte area for storing
Program Data Operation Chart
Number of Writes (n)
Original Data
Additional program data
Clear PSU1 (2) bit in FLMCR1 (2)
Write pulse application subroutine
Set PSU1 (2) bit in FLMCR1 (2)
Reprogram data area
Wait (z1) μs or (z2) μs or (z3) μs
of programming. See Note 7 for the pulse widths. When the additional program
data is programmed, a write pulse of (z3) μs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied.
address written to must be H'00 or H'80. A 128-byte data transfer must
be performed even if writing fewer than 128 bytes; in this case, H'FF
data must be written to the extra addresses.
programming loop will be subjected to additional programming if they
fail the subsequent verify operation.
reprogram data, and a 128-byte area for storing additional program data
should be provided in RAM. The contents of the reprogram data and
additional program data areas are modified as programming proceeds.
Program data area
Clear P1 (2) bit in FLMCR1 (2)
Set P1 (2) bit in FLMCR1 (2)
area (128 bytes)
(D)
programming.
0
1
Sub-routine write pulse
(128 bytes)
(128 bytes)
1000
998
999
10
11
12
13
1
2
3
4
5
6
7
8
9
.
.
.
RAM
Disable WDT
Enable WDT
Wait (α) μs
Wait (β) μs
Wait (y) μs
End sub
Verify Data
(V)
0
1
0
1
Write Time (z) μs
Reprogram Data
*6
Figure 19.71 Program/Program-Verify Flowchart
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
.
.
.
(X)
1
0
1
*6
*5 *6
*6
*6
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Increment address
Comments
Store 128-byte program data in program
NG
data area consecutively to flash memory
additional program data area in RAM to
Write 128-byte data in RAM reprogram
Transfer reprogram data to reprogram
Additional program data computation
H'FF dummy write to verify address
data area and reprogram data area
Transfer additional program data to
Sequentially write 128-byte data in
Clear SWE1 (2) bit in FLMCR1 (2)
Clear PV1 (2) bit in FLMCR1 (2)
Set SWE1 (2) bit in FLMCR1 (2)
Set PV1 (2) bit in FLMCR1 (2)
Reprogram data computation
additional program data area
(z3) µs additional write pulse
Start of programming
Additional Program Data Operation Chart
End of programming
Read data = verify
Reprogram
Read verify data
(z1) μs or (z2) μs
data verification
Data (X')
flash memory
Write Pulse
Wait (x) μs
Wait (γ) μs
Wait (ε) μs
completed?
Write pulse
Wait (η) μs
Wait (θ) μs
data area
128-byte
0
1
m = 0?
m = 0
6 ≥ n ?
6 ≥ n ?
data?
n = 1
Start
OK
OK
OK
OK
OK
Sub-routine-call
Verify Data
(V)
0
1
0
1
NG
NG
NG
NG
Program Data (Y)
Additional
*6
*6
*4
*1
See Note 7 for pulse width
*2
*3
*4
*1
*4
*6
*6
*6
*6
*6
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
0
1
Clear SWE1 (2) bit in FLMCR1 (2)
m = 1
Programming failure
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
Wait (θ) μs
n ≥ N?
OK
*6
Comments
NG
n ← n + 1
*6