HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 216

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.5.6
Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4
states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or
disabling of wait insertion, and do not affect the number of access states. When the corresponding
bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle.
The 4 states of the basic timing consist of one T
output cycle), and two T
Rev.6.00 Sep. 27, 2007 Page 186 of 1268
REJ09B0220-0600
Note: n = 2 to 5
Read
Write
Basic Timing
CAS, LCAS
CSn (RAS)
HWR (WE)
HWR (WE)
D
D
A
15
15
23
to D
to D
to A
c
φ
0
0
0
(column address output cycle) states, T
Figure 6.15 Basic Access Timing
T
p
p
(precharge cycle) state, one T
Row
T
r
T
c1
c1
and T
Column
c2
.
T
r
c2
(row address