HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 290

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.5.3
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one
byte or word is transferred in response to a single transfer request, and this is executed the number
of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.7 summarizes register functions in idle mode.
Table 7.7
Register
23
23
Legend:
MAR:
IOAR:
ETCR: Execute transfer count register
DTDIR: Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
Rev.6.00 Sep. 27, 2007 Page 260 of 1268
REJ09B0220-0600
H'FF
Memory address register
I/O address register
15
15
Idle Mode
MAR
Register Functions in Idle Mode
IOAR
ETCR
0
0
0
DTDIR = 0 DTDIR = 1 Initial Setting
Source
address
register
Destination
address
register
Transfer counter
Function
Destination
address
register
Source
address
register
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Operation
Fixed
Fixed
transfer; transfer
ends when count
reaches H'0000