HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 615

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.2.2
Note: * Only 0 can be written, to clear the flag.
TCSR is an 8-bit readable/writable * register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in
interval timer mode. This flag cannot be set during watchdog timer operation.
Bit 7
OVF
0
1
Note: * When OVF is polled and the interval timer interrupt is disabled, OVF = 1 must be read at
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF
signal *
Bit
Initial value :
R/W
1
least twice.
section 13.2.4, Notes on Register Access.
when TCNT overflows.
Timer Control/Status Register (TCSR)
Description
[Clearing condition]
Cleared by reading TCSR when OVF = 1 * , then writing 0 to OVF
[Setting condition]
Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode
:
:
R/(W) *
OVF
7
0
WT/IT
R/W
6
0
TME
R/W
5
0
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4
1
Rev.6.00 Sep. 27, 2007 Page 585 of 1268
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1
Section 13 Watchdog Timer
CKS2
R/W
2
0
REJ09B0220-0600
CKS1
R/W
1
0
(Initial value)
CKS0
R/W
0
0