HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 17

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

Table 7
Symbol
DM, LDM, UDM Input
BA[1:0]
A[13:0]
DQx
DQS, (DQS)
LDQS, (LDQS),
UDQS,(UDQS)
RDQS, (RDQS) Input/
NC
V
V
V
V
V
V
V
(BA2), A[15:14]
Data Sheet
DDQ
SSQ
DDL
SSDL
DD
SS
REF
Input/Output Functional Description
Type
Input
Input
Input/
Output
Input/
Output
Output
—
Supply DQ Power Supply: 1.8 V
Supply DQ Ground
Supply DLL Power Supply: 1.8 V
Supply DLL Ground
Supply Power Supply: 1.8 V
Supply Ground
Supply Reference Voltage
—
Function
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled high coincident with that input data during a Write access. DM is
sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. LDM and UDM are the input mask signals for 16
components and control the lower or upper bytes. For 8 components the data mask
function is disabled, when RDQS / RQDS are enabled by EMRS(1) command.
Bank Address Inputs: BA[1:0] define to which bank an Activate, Read, Write or
Precharge command is being applied. BA[1:0] also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS(1) cycle.
Address Inputs: Provides the row address for Activate commands and the column
address and Auto-Precharge bit A10 (=AP) for Read/Write commands to select one
location out of the memory array in the respective bank. A10 (=AP) is sampled during
a Precharge command to determine whether the Precharge applies to one bank
(A10=low) or all banks (A10=high). If only one bank is to be precharged, the bank is
selected by BA[1:0]. The address inputs also provide the op-code during Mode
Register Set commands.
Row address A13 is used on 4 and 8 components only.
Data Inputs/Output: Bi-directional data bus. DQ[0:3] for 4 components, DQ[0:7] for
Data Strobe: output with read data, input with write data. Edge aligned with read data,
centered with write data. For the 16, LDQS corresponds to the data on LDQ[7:0];
UDQS corresponds to the data on UDQ[7:0]. The data strobes DQS, LDQS, UDQS
may be used in single ended mode or paired with the optional complementary signals
DQS, LDQS, UDQS to provide differential pair signaling to the system during both
reads and writes. An EMRS(1) control bit enables or disables the complementary data
strobe signals.
Read Data Strobe: For the 8 components a RDQS, RDQS pair can be enabled via
the EMRS(1) for read timing. RDQS, RDQS is not supported on 4 and 16
components. RDQS, RDQS are edge-aligned with read data. If RDQS, RDQS is
enabled, the DM function is disabled on 8 components.
No Connect: no internal electrical connection is present
BA2, A[15:14] are additional address pins for future generation DRAMs and are not
connected on this component.
8 components, DQ[0:15] for 16 components.
±
0.1 V
±
±
17
0.1 V
0.1 V
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512[400/800/160]A[C/F]–[3.7/5]
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05
Overview