HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 81

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

Table 40
Symbol Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1) V
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
3) Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
7) Min (
8) For input frequency change during DRAM operation, see
Data Sheet
RFC
RCD
RP
RRD
CCD
WR
DAL
WTR
RTP
XARD
XARDS
XP
XSRD
XSNR
CKE
REFI
OIT
DELAY
powered down and then restarted through the specified initialization sequence before normal operation can continue.
differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. For other slew
rates see
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS,
For
recognized as LOW.
this value can be greater than the minimum specification limits for
DDQ
t
IS
t
= 1.8V
CL
,
Auto-Refresh to Active/Auto-Refresh
command period
Active to Read or Write delay
(with and without Auto-Precharge)
Precharge command period
Active bank A to Active bank B command
period
CAS A to CAS B command period
Write recovery time
Auto-Precharge write recovery +
precharge time
Internal Write to Read command delay
Internal Read to Precharge command
delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to Read command
Exit Self-Refresh to non-Read command
CKE minimum high and low pulse width
Average periodic refresh Interval
OCD drive mode output delay
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t
,
iH
t
,
CH
Chapter 8
Timing Parameter by Speed Grade - DDR2-400 & DDR2-533
t
DS
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
±
,
t
0.1V;
DH
input reference levels see
V
of this datasheet.
DD
= 1.8V
±
0.1V) See notes
V
REF
V
TT
Electrical Characteristics & AC Timing - Absolute Specification
Chapter 8.3
stabilizes. During the period before
. See
3)4)5)6)
Chapter 8
–5
DDR2–400 3–3–3
Min.
105
15
15
7.5
10
2
15
WR +
10
7.5
2
6 - AL
2
200
t
3
—
—
0
t
RFC
IS
81
Chapter 2.12
+
of this datasheet.
t
+10
CK
+
t
512-Mbit Double-Data-Rate-Two SDRAM
RP
for the reference load for timing measurements.
t
IH
HYB18T512[400/800/160]A[C/F]–[3.7/5]
t
CL
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7.8
3.9
12
—
and
of this datasheet.
t
CH)
.
1)2)3)4)5)6)
–3.7
DDR2–533 4–4–4
Min.
105
15
15
7.5
10
2
15
WR +
7.5
7.5
2
6 - AL
2
200
t
3
—
—
0
t
RFC
IS
V
+
t
t
REF
+10
IS
CK
,
+
t
t
RP
iH
stabilizes, CKE = 0.2 x
t
IH
,
t
DS
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7.8
3.9
12
––
,
09112003-SDM9-IQ3P
t
DH
is
Rev. 1.13, 2004-05
V
REF
Unit Notes
ns
ns
ns
ns
ns
t
ns
t
ns
ns
t
t
t
t
ns
t
µ
µ
ns
ns
.
CK
CK
CK
CK
CK
CK
CK
s
s
17)
18)
19)
20)
21)
22)
23)
23)
24)25)
26)
27)
V
DDQ
is