HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 23

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

Figure 8
2.2.2
For application flexibility, burst length, burst type, CAS
latency, DLL reset function, write recovery time (
are user defined variables and must be programmed
with a Mode Register Set (MRS) command.
Additionally, DLL disable function, additive CAS
latency, driver impedance, On Die Termination (ODT),
single-ended strobe and Off Chip Driver impedance
adjustment (OCD) are also user defined variables and
must be programmed with an Extended Mode Register
Set (EMRS) command.
Contents of the Mode Register (MRS) or Extended
Mode Registers (EMRS(#)) can be altered by re-
executing the MRS and EMRS Commands. If the user
chooses to modify only a subset of the MRS or EMRS
variables, all variables must be redefined when the
MRS or EMRS commands are issued.
Also any programming of EMRS(2) or EMRS(3) must
be followed by programming of MRS and EMRS(1).
After initial power up, all MRS and EMRS Commands
2.2.2.1
The mode register stores the data for controlling the
various operating modes of DDR2 SDRAM. It programs
CAS latency, burst length, burst sequence, test mode,
DLL reset, Write Recovery (WR) and various vendor
specific options to make DDR2 SDRAM useful for
various applications.
The default value of the mode register is not defined,
therefore the mode register must be written after
power-up for proper operation. The mode register is
written by asserting low on CS, RAS, CAS, WE,
BA[1:0], while controlling the state of address pins
A[13:0]. The DDR2 SDRAM should be in all bank
precharged (idle) mode with CKE already high prior to
writing into the mode register. The mode register set
command cycle time (
write operation to the mode register. The mode register
contents can be changed using the same command
Data Sheet
CK, CK
CKE
ODT "low"
NOP
400 ns
Initialization Sequence after Power Up
Programming the Mode Register and Extended Mode Registers
DDR2 SDRAM Mode Register Set (MRS)
PRE
ALL
tRP
EMRS(2)
t
MRD
tMRS
) is required to complete the
EMRS(3)
tMRS
with DLL enable
Register(1) Set
Extended
EMRS(1)
Mode
tMRS
DLL reset
Register
Set with
MRS
Mode
tMRS
t
WR
PRE
ALL
)
tRP
23
min. 200 cycles to lock the DLL
must be issued before read or write cycles may begin.
All banks must be in a precharged state and CKE must
be high at least one cycle before the Mode Register Set
Command can be issued. Either MRS or EMRS
Commands are activated by the low signals of CS,
RAS, CAS and WE at the positive edge of the clock.
When both bank addresses BA[1:0] are low, the DDR2
SDRAM enables the MRS command. When the bank
addresses BA0 is high and BA1 is low, the DDR2
SDRAM enables the EMRS(1) command.
The address input data during this cycle defines the
parameters to be set as shown in the MRS and EMRS
table. A new command may be issued after the mode
register set command cycle time (
MRS, EMRS and DLL Reset do not affect array
contents, which means reinitialization including those
can be executed any time after power-up without
affecting array contents.
and clock cycle requirements during normal operation
as long as all banks are in the precharged state. The
mode register is divided into various fields depending
on functionality.
Burst length is defined by A[2:0] with options of 4 and 8
bit burst length. Burst address sequence type is defined
by A3 and CAS latency is defined by A[6:4]. A7 is used
for test mode and must be set to low for normal MRS
operation. A8 is used for DLL reset. A[11:9] are used for
write recovery time (
mode. With address bit A12 two Power-Down modes
can be selected, a “standard mode” and a “low-power”
Power-Down mode, where the DLL is disabled.
Address bit A13 and all “higher” address bits have to
be set to “low” for compatibility with other DDR2
memory products with higher memory densities.
1st Auto
refresh
512-Mbit Double-Data-Rate-Two SDRAM
tRFC
HYB18T512[400/800/160]A[C/F]–[3.7/5]
2nd Auto
refresh
tRFC
DLL reset
Register
Set w/o
MRS
Mode
tMRS
t
OCD Drive(1)
WR
OCD default
EMRS(1)
OCD
) definition for Auto-Precharge
or
Follow OCD
flowchart
Functional Description
09112003-SDM9-IQ3P
calibration
mode exit
EMRS(1)
OCD
t
OCD
MRD
Rev. 1.13, 2004-05
tMRS
).
Command
Any