HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 59

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

Figure 53
Note:
1. Device must be in the “All banks idle” state before
2.
2.10
Power-down is synchronously entered when CKE is
registered low, along with NOP or Deselect command.
CKE is not allowed to go low while mode register or
extended mode register command time, or read or write
operation is in progress. CKE is allowed to go low while
any other operation such as row activation, Precharge,
Auto-Precharge or Auto-Refresh is in progress, but
power-down
finishing those operations.
The DLL should be in a locked state when power-down
is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation. DRAM
design guarantees it’s DLL in a locked state with any
CKE intensive operations as long as DRAM controller
complies with DRAM specifications.
If power-down occurs when all banks are precharged,
this mode is referred to as Precharge Power-down; if
power-down occurs when there is a row active in any
bank, this mode is referred to as Active Power-down.
For Active Power-down two different power saving
modes can be selected within the MRS register,
address bit A12. When A12 is set to “low” this mode is
Data Sheet
ODT
CMD
CKE
CK/CK
entering Self Refresh mode.
t
with Auto-Precharge command.
XSRD
( 200
T0
Self Refresh Timing
Power-Down
I
DD
t
CK
specification will not be applied until
tis
) has to be satisfied for a Read or a Read
T1
T2
tAOFD
T3
tRP
Self Refresh
tis
Entry
T4
CK/CK may
be halted
59
tCKE
T5
3. t
4. Since CKE is an SSTL input,
referred as “standard active power-down mode” and a
fast power-down exit timing defined by the
parameter can be used. When A12 is set to “high” this
mode is referred as a power saving “low power active
power-down mode”. This mode takes longer to exit
from the power-down mode and the
parameter has to be satisfied.
Entering power-down deactivates the input and output
buffers, excluding CK, CK, ODT and CKE. Also the DLL
is disabled upon entering Precharge Power-down or
slow exit active power-down, but the DLL is kept
enabled during fast exit active power-down. In power-
down mode, CKE low and a stable clock signal must be
maintained at the inputs of the DDR2 SDRAM, and all
other input signals are “Don’t Care”. Power-down
duration is limited by 9 times
The power-down state is synchronously exited when
CKE is registered high (along with a NOP or Deselect
command). A valid, executable command can be
applied with power-down exit latency,
t
are defined in
XARDS
512-Mbit Double-Data-Rate-Two SDRAM
Read or a Read with Auto-Precharge command
maintained during Self Refresh.
XSNR
HYB18T512[400/800/160]A[C/F]–[3.7/5]
, after CKE goes high. Power-down exit latencies
CK/CK must
be stable
has to be satisfied for any command except a
Table
tis
>= tXSNR
Tm
NOP
40.
>=tXSRD
Command
Non-Read
t
Tn
REFI
Functional Description
09112003-SDM9-IQ3P
V
of the device.
REF
Rev. 1.13, 2004-05
t
XARDS
must be
t
XP
,
t
Command
t
XARD
timing
XARD
Read
Tr
or
timing