HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 45

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

Figure 34
The seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every BL/2
number of clocks. This operation is allowed regardless of same or different banks as long as the banks are
activated.
2.6.5
One write data mask input (DM) for 4 and 8
components and two write data mask inputs (LDM,
UDM) for 16 components are supported on DDR2
SDRAM’s, consistent with the implementation on DDR
SDRAM’s. It has identical timings on write operations
as the data bits, and though used in a uni-directional
manner, is internally loaded identically to data bits to
Figure 35
Data Sheet
C M D
C K , C K
D Q S ,
D Q S
D Q
W R IT E A
T0
Seamless Write Operation Example 2: RL = 3, WL = 2, BL = 8, non interrupting
Write Data Mask
Write Data Mask Timing
W L = R L - 1 = 2
DQS,
DQS
DQ
DM
T1
N O P
DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A5 DIN A7 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN B6 DIN B7
T2
N O P
T3
t
DS
N O P
t
WPRE
Mask
D
t
DQSH
DQS
W R IT E B
DQS
T4
Mask
45
D
t
DQSL
insure matched system timing. Data mask is not used
during read cycles. If DM is high during a write burst
coincident with the write data, the write data bit is not
written to the memory. For 8 components the DM
function is disabled, when RDQS / RDQS are enabled
by EMRS(1).
T5
t
N O P
512-Mbit Double-Data-Rate-Two SDRAM
DH
HYB18T512[400/800/160]A[C/F]–[3.7/5]
Mask
D
T6
N O P
Mask
D
t
WPST
T7
N O P
don't care
SBW_BL8
T8
Functional Description
N O P
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05