K4X56163PE Samsung semiconductor, K4X56163PE Datasheet

K4X56163PE

Manufacturer Part Number

K4X56163PE

Description

16M x16 Mobile DDR SDRAM

Manufacturer

Samsung semiconductor

Datasheet

1.K4X56163PE.pdf (48 pages)

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Column address configuration

DM is internally loaded to match DQ and DQS identically.

K4X56163PE-L(F)G

16M x16 Mobile DDR SDRAM

Operating Frequency

*CL : CAS Latency

FEATURES

• 1.8V power supply, 1.8V I/O power

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

• MRS cycle with address key programs

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).

• Data I/O transactions on both edges of data strobe, DM for masking.

• Edge aligned data output, center aligned data input.

• No DLL; CK to DQS is not synchronized.

• LDM/UDM for write masking only.

• 7.8us auto refresh duty cycle.

• CSP package.

- CAS Latency ( 3 )

- Burst Length ( 2, 4, 8 )

- Burst Type (Sequential & Interleave)

- Partial Self Refresh Type ( Full, 1/2, 1/4 array )

- Internal Temperature Compensated Self Refresh

- Driver strength ( 1, 1/2, 1/4, 1/8 )

Organization

Speed @CL3

16Mx16

Row Address

A0 ~ A12

DDR200

100Mhz

Mobile-DDR SDRAM

Column Address

DDR133

66Mhz

A0-A8

March 2004

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