K4X56163PE Samsung semiconductor, K4X56163PE Datasheet - Page 6

• Manufacturer Part Number: K4X56163PE
• Description: 16M x16 Mobile DDR SDRAM
• Manufacturer: Samsung semiconductor

K4X56163PE-L(F)G
Mode Register Definition
Mode Register Set(MRS)
The mode register is designed to support the various operating modes of DDR SDRAM. It includes CAS latency, addressing mode,
burst length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the
mode register is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM. The mode reg-
ister is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to
writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going
low is written in the mode register.
power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed
with the same command and four clock cycles. This command must be issued only when all banks are in the idle state. If mode reg-
ister is changed, extended mode register automatically is reset and come into default state. So extended mode register must be set
again. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode
uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. BA0 and BA1 must be set to low
for normal DDR SDRAM operation.
BA1
0
BA0
0
A12
A
0
0
0
0
1
1
1
1
0
6
A11
A
0
0
1
1
0
0
1
1
0
5
A10
Two
A
0
1
0
1
0
1
0
1
0
4
clock cycles are required to complete the write operation in the mode register. Even if the
A9
0
Figure.2 Mode Register Set
Figure.2 Mode Register Set
CAS Latency
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
A8
3
0
A7
0
6
A6
CAS Latency
Burst Length
A
0
0
0
0
1
1
1
1
A5
2
A
0
0
1
1
0
0
1
1
A
A4
0
1
1
3
A
0
1
0
1
0
1
0
1
Burst Type
A3
Mobile-DDR SDRAM
0
Sequential
Interleave
BT
Sequential
A2
Reserve
Reserve
Reserve
Reserve
Reserve
Burst Length
2
4
8
A1
Burst type
A0
Interleave
Reserve
Reserve
Reserve
Reserve
Reserve
March 2004
Address Bus
2
4
8
Mode Register