K4X56163PE Samsung semiconductor, K4X56163PE Datasheet - Page 17

• Manufacturer Part Number: K4X56163PE
• Description: 16M x16 Mobile DDR SDRAM
• Manufacturer: Samsung semiconductor

Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access
is allowed. A write recovery time(tWR) is required from the last data to precharge command. When precharge command is
asserted, any residual data from the burst write cycle must be masked by DM.
Command
Max tDQSS
Min tDQSS
Precharge timing for Write operations in DRAMs requires enough time to allow ’’write recovery’’ which is the time required by a DRAM
core to properly store a full ’’0’’ or ’’1’’ level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to
indicate the required amount of time between the last valid write operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled
by the input clock. Inside the SDRAM, the data path is eventually synchronized with the address path by switching clock domains
from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated
after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal
write operation, i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and ends on the rising clock
edge that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time
K4X56163PE-L(F)G
< Burst Length=8 >
CK, CK
DQS
DQs
DM
DQS
DQs
DM
recovery is defined by tWR.
between the last valid write data and the rising clock edge on which the Precharge command is given. During this time, the DQS
input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR.
NOP
0
WRITE A
t
Figure.11 Write interrupted by a precharge and DM timing
WPRES
t
t
DQSSmin
WPRES
1
t
t
DQSSmax
WPREH
t
Dina
WPREH
NOP
0
Dina
Dina
2
0
1
Dina
Dina
1
2
NOP
Dina
Dina
3
2
3
Dina
Dina
3
4
17
NOP
Dina
Dina
4
4
5
Dina
Dina
tWR
5
6
tWR
NOP
Dina
Dina
5
6
7
Dina
Precharge
7
Mobile-DDR SDRAM
6
WRITE B
t
WPRES
t
DQSSmin
7
t
WPRES
t
DQSSmax
t
WPREH
Dinb
t
WPREH
0
NOP
Dinb
Dinb
March 2004
8
0
1
Dinb
Dinb
1
2