K4X56163PE Samsung semiconductor, K4X56163PE Datasheet - Page 15

• Manufacturer Part Number: K4X56163PE
• Description: 16M x16 Mobile DDR SDRAM
• Manufacturer: Samsung semiconductor

Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge
intervals. A precharge command to output disable latency is equivalent to the CAS latency.
1.
2.
3.
4.
K4X56163PE-L(F)G
CAS Latency=3
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read
burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when
a new Bank Activate command may be issued to the same bank.
Command
CK, CK
< Burst Length=8, CAS Latency=3 >
For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate
command may be issued to the same bank after tRP (RAS Precharge time).
When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data
word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after
tRP.
For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During
Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external
Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.
For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between
a Precharge command and a new Bank Activate command to the same bank equals tRP/tCK (where tCK is the clock cycle time)
with the result rounded up to the nearest integer number of clock cycles. (Note that rounding to X.5 is not possible since the
Precharge and Bank Activate commands can only be given on a rising clock edge).In all cases, a Precharge operation cannot
be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with
autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same
timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.
DQS
DQs
READ
0
1tCK
Precharge
Figure.9 Read interrupted by a precharge timing
1
NOP
t
RPRE
2
t
SAC
Dout 0 Dout 1 Dout 2 Dout 3
NOP
3
15
NOP
4
Interrupted by precharge
Dout 4 Dout 5 Dout 6 Dout 7
NOP
5
Mobile-DDR SDRAM
NOP
6
NOP
7
March 2004
NOP
8