K4X56163PE Samsung semiconductor, K4X56163PE Datasheet - Page 31

• Manufacturer Part Number: K4X56163PE
• Description: 16M x16 Mobile DDR SDRAM
• Manufacturer: Samsung semiconductor

DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
Notes:
1. IDD specifications are tested after the device is properly intialized.
2. Input slew rate is 1V/ns.
K4X56163PE-L(F)G
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Parameter
Symbol
I
I
I
I
I
CC2
CC2
CC3
CC3
I
I
I
I
I
CC
CC2
CC3
CC
CC2
CC3
I
I
I
CC
CC
CC0
4W
4R
PS
NS
PS
NS
5
6
N
N
P
P
t RC = t RCmin ; t CK = t CKmin ; CKE is HIGH; CS is HIGH
between valid commands;
address inputs are SWITCHING; data bus inputs are STA-
BLE
all banks idle, CKE is LOW; CS is HIGH, t CK = t CKmin ;
address and control inputs are SWITCHING; data bus inputs
are STABLE
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK =
HIGH; address and control inputs are SWITCHING; data
bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, t CK = t CKmin
;address and control inputs are SWITCHING; data bus
inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK =
HIGH; address and control inputs are SWITCHING; data
bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, t CK = t CKmin
;address and control inputs are SWITCHING; data bus
inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK
= HIGH;address and control inputs are SWITCHING; data
bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, t CK = t CKmin
;address and control inputs are SWITCHING; data bus
inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK
= HIGH;
address and control inputs are SWITCHING; data bus inputs
are STABLE
one bank active; BL = 4; CL = 3; t CK = t CKmin ; continuous
read bursts; I OUT = 0 mA
address inputs are SWITCHING; 50% data change each
burst transfer
one bank active; BL = 4; t CK = t CKmin ; continuous write
bursts;address inputs are SWITCHING; 50% data change
each burst transfer
t RC = t RFCmin ; t CK = t CKmin ; burst refresh; CKE is
HIGH;address and control inputs are SWITCHING; data bus
inputs are STABLE
CKE is LOW; t CK = t CKmin ;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
Test Condition
SS
= 0V, Temp = -25 to 85°C)
31
TCSR Range
Full Array
1/2 Array
1/4 Array
Mobile-DDR SDRAM
DDR200
Max 40
150
125
115
30
10
65
65
80
8
4
6
0.3
0.3
3
1
DDR133
Max 85
400
300
250
30
10
55
55
80
8
4
6
March 2004
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
uA