K4X56163PE Samsung semiconductor, K4X56163PE Datasheet - Page 13

• Manufacturer Part Number: K4X56163PE
• Description: 16M x16 Mobile DDR SDRAM
• Manufacturer: Samsung semiconductor

Burst Write Operation
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The
address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The
first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS
from the rising edge of the clock(CK) that the write command is issued. The remaining data inputs must be supplied on each subse-
quent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data
supplied to the DQ pins will be ignored.
1. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown
K4X56163PE-L(F)G
< Burst Length=4 >
Command
(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.
If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
DQS
DQs
CK
CK
NOP
0
WRITEA
t
WPRES*1
1
t
DQSSmax
*1
Figure.6 Burst write operation timing
NOP
Din 0 Din 1 Din 2
2
WRITEB
3
*1
Din 3
13
NOP
Din 0 Din 1 Din 2
4
NOP
5
Din 3
Mobile-DDR SDRAM
NOP
6
NOP
7
March 2004
NOP
8