AK4691EG AKM [Asahi Kasei Microsystems], AK4691EG Datasheet - Page 21

• Manufacturer Part Number: AK4691EG
• Description: 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

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There are the following four clock modes to interface with external devices
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
Don’t Care
Note 47. If this mode is selected, the invalid clocks are output from the MCKO pin when MCKO bit is “1”.
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
■
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4691 is power-down mode (PDN pin = “L”) and exits reset state, the AK4691 is slave mode. After exiting reset state,
the AK4691 is set to master mode by changing M/S bit = “1”.
When the AK4691 is used by master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The
LRCK and BICK pins of the AK4691 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to
avoid the floating state.
MS0672-E-00
System Clock
Master Mode/Slave Mode
(Note
47)
Table 3. Select Master/Slave Mode
Table 1. Clock Mode Setting (x: Don’t care)
M/S bit
Table 2. Clock pins state in Clock Mode
0
1
OPERATION OVERVIEW
MCKO bit
PMPLL bit
0
1
0
1
0
0
1
1
1
0
0
Master Mode
Slave Mode
- 21 -
Mode
Selected by
Selected by
MCKO pin
PS1-0 bits
PS1-0 bits
L
L
L
L
M/S bit
1
0
0
0
1
(default)
(Table
PLL3-0 bits
PLL3-0 bits
Selected by
Selected by
Selected by
MCKI pin
FS3-0 bits
GND
1,
Table
PLL3-0 bits
Table 4
Table 4
Table 4
(Selected by
(Selected by
x
x
BCKO bit)
BCKO bit)
2).
BICK pin
(≥ 32fs)
(≥ 32fs)
Output
Output
Input
Input
Figure 13
Figure 14
Figure 15
Figure 16
LRCK pin
Figure
Output
Input
Input
Input
(1fs)
(1fs)
(1fs)
(1fs)
[AK4691]
-
2007/11