AK4691EG AKM [Asahi Kasei Microsystems], AK4691EG Datasheet - Page 44

• Manufacturer Part Number: AK4691EG
• Description: 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

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In FADEIN Mode, the IVL/R values increase gradually by the step set by FDATT1-0 bits when FDIN bit changes from
“0” to “1”. The FADEIN period is set by REF7-0, FDATT1-0
operation is executed by the zero crossing detection. The operation stops when the IVL/R values become the REF value or
the limiter detection level (LMTH1-0). If the limiter operation is executed during FADAIN period, the FADEIN
operation stops and the ALC operation starts.
NOTE: When FDIN and FDOUT bits are set to “1” at the same time, FADEOUT operation is prior to FADEIN operation.
(1) WR(IVL/R7-0 bits = 00H) : IVL/R are changed to “MUTE”.
(2) WR (ALC bit = FDIN bit = “0”): The ALC operation is disabled. To start the FADEIN operation, FDIN bit is written
(3) WR (ALC bit = FDIN bit = “1”): The FADEIN operation starts. The IVL/R is fade-in from MUTE state.
(4) The FADEIN operation is repeated until the limiter detection level (LMTH1-0 bits) or the reference level (REF7-0
(5) FADEIN time is set by REF7-0, FDTM1-0, and FDATT bits
MS0672-E-00
FADEIN Mode
in “0”.
bits). After completing the FADEIN operation, the ALC operation starts.
e.g. REF7-0 = E1H(225 dec), FDTM1-0 = “01” (= 42.7ms @ fs = 48kHz), FDATT1-0 = 2 step
FDTM1 bit
(225 x FDTM1-0) / FDATT1-0 = 225 x 42.7ms /2 = 4.8s
0
0
1
1
IVL/R7-0 bits
SDTO1, 2
ALC bit
FDIN bit
FDTM0 bit
Figure 27. Example for controlling sequence in FADEIN operation
0
1
0
1
XXH
FDATT1 bit
Table 35. FADEIN/OUT ATT Step Setting
(1)
0
0
1
1
Table 34. FADEIN/OUT Period
1024/fs
2048/fs
2304/fs
2560/fs
(2)
00H
FDATT0 bit
- 44 -
0
1
0
1
128ms
256ms
288ms
320ms
8kHz
(Table
FADEIN/OUT Period
35) and FDTM1-0
ATT STEP
(3)
1
2
3
4
32kHz
64ms
32ms
72ms
80ms
(5)
(4)
(default)
(Table
21.3ms
42.7ms
53.3ms
48kHz
48ms
34) bits. The FADEIN
(default)
[AK4691]
2007/11