AK4691EG AKM [Asahi Kasei Microsystems], AK4691EG Datasheet - Page 24

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AK4691EG

Manufacturer Part Number
AK4691EG
Description
4ch ADC + 2ch DAC with MIC/HP/SPK-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the
MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by
PS1-0 bits
by BCKO bit
MS0672-E-00
PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
(Table
(Table
9) and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs,
10).
Mode
Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
0
1
2
3
AK4691
Table 10. BICK Output Frequency at Master Mode
BCKO bit
MCKI
MCKO
BICK
LRCK
SDTO1/2
SDTI
PS1 bit
0
1
0
0
1
1
Figure 13. PLL Master Mode
256fs/128fs/64fs/32fs
32fs, 64fs
BICK Output
PS0 bit
1fs
Frequency
- 24 -
0
1
0
1
32fs
64fs
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
MCKO pin
MCLK
BCLK
LRCK
SDTI1/2
SDTO
256fs
128fs
64fs
32fs
(default)
DSP or μP
(default)
[AK4691]
2007/11

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