AK4691EG AKM [Asahi Kasei Microsystems], AK4691EG Datasheet - Page 53

• Manufacturer Part Number: AK4691EG
• Description: 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

Note 53. Rising time of stereo line output (0.9 x LVCM)
Note 54. Falling time of stereo line output (This time is until the voltage between 220Ω and 20kΩ resistors as shown in
[Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)]
E.g. In case of LVDD = 3.6V
MS0672-E-00
(1) Set LOPS bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO bit = “1”. Stereo line output exits the power-down mode.
(3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode.
(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO bit = “1”. Stereo line output enters power-down mode.
(6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode.
P M L O b it
L O P S b it
L O U T , R O U T p in s
Figure 34
LOUT and ROUT pins rise up to LVCM voltage. Rise time is 200ms (max 300ms) at C=1μF.
Stereo line output is enabled.
LOUT and ROUT pins fall down to VSS4. Fall time is 200ms (max 300ms) at C=1μF.
Figure 35. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)
becomes less than 50mV.)
( 1 )
LVDD
3.6V
5.5V
( 2 )
Table 46. Rising / Falling time of stereo line output
≥ 3 0 0 m s
Rising Time
200ms
220ms
typ.
( 3 )
(Note
300ms
400ms
N o r m a l O u tp u t
max
- 53 -
53)
Falling Time
200ms
260ms
typ.
(Note
( 4 )
300ms
440ms
max.
54)
( 5 )
≥ 3 0 0 m s
( 6 )
[AK4691]
2007/11