AK4691EG AKM [Asahi Kasei Microsystems], AK4691EG Datasheet - Page 47

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AK4691EG

Manufacturer Part Number
AK4691EG
Description
4ch ADC + 2ch DAC with MIC/HP/SPK-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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When writing to the IVL7-0 and IVR7-0 bits continuously, the control register should be written in an interval more than
zero crossing timeout. If not, IVL and IVR are not changed since zero-crossing counter is reset at every write operation. If
the same register value as the previous write operation is written to IVL and IVR, this write operation is ignored and
zero-crossing counter is not reset. Therefore, IVL and IVR can be written in an interval less than zero crossing timeout.
(1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts.
(2) Writing to IVL and IVR registers (0EH, 10H) is ignored during ALC operation. After ALC is disabled, the IVOL
The AK4691 includes the digital de-emphasis filter (tc = 50/15μs) by IIR filter. Setting the DEM1-0 bits enables the
de-emphasis filter
MS0672-E-00
De-emphasis Filter
changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1”
with an interval more than zero crossing timeout period after ALC bit = “0”.
ALC bit
ALC Status
IVL7-0 bits
IVR7-0 bits
Internal IVL
Internal IVR
(Table
37).
Figure 29. IVOL value during ALC operation (GSEL bit = “0”)
DEM1 bit
C6H(+20dB)
E1H(+30dB)
0
0
1
1
Disable
Table 37. De-emphasis Control
DEM0 bit
(1)
0
1
0
1
E1(+30dB) --> F1(+36dB)
E1(+30dB) --> F1(+36dB)
- 47 -
E1H(+30dB)
C6H(+20dB)
44.1kHz
48kHz
32kHz
Enable
Mode
OFF
(default)
(2)
C6H(+20dB)
E1(+30dB)
Disable
[AK4691]
2007/11

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