AK4691EG AKM [Asahi Kasei Microsystems], AK4691EG Datasheet - Page 61

• Manufacturer Part Number: AK4691EG
• Description: 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

(2) I
The AK4691 supports the fast-mode I
connected to (TVDD2 + 0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 42
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit).
This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits
(Figure
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4691. The format is MSB first, and those most
significant 3-bits are fixed to zeros
first, 8bits
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition
The AK4691 can perform more than one byte write operation per sequence. After receiving the third byte the AK4691
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only be changed when the clock signal on the SCL line is LOW
conditions.
MS0672-E-00
2
C-bus Control Mode (I2CN pin = “L”)
43). If the slave address matches that of the AK4691, the AK4691 generates an acknowledge and the operation is
shows the data transfer sequence for the I
(Figure
SDA
45). The AK4691 generates an acknowledge after each byte has been received. A data transfer is
S
T
A
R
T
S
Slave
Address
D7
0
0
(Figure
R/W="0"
Figure 42. Data Transfer Sequence at the I
A
C
K
49). A R/W bit value of “1” indicates that the read operation is to be executed. A “0”
D6
0
0
(Figure
(Figure
Figure 45. Byte Structure after the second byte
Sub
Address(n)
2
(The CAD0 should match with CAD0 pin)
C-bus (max: 400kHz). Pull-up resistors at the SCL and SDA pins should be
44). The data after the second byte contains control data. The format is MSB
48).
A5
D5
1
Figure 44. The Second Byte
Figure 43. The First Byte
C
A
K
2
C-bus mode. All commands are preceded by a START condition. A
Data(n)
A4
D4
0
- 61 -
A
C
K
A3
D3
0
Data(n+1)
(Figure
2
A2
D2
C-Bus Mode
1
C
A
K
50) except for the START and STOP
CAD0
A1
D1
A
C
K
Data(n+x)
R/W
A0
D0
(Figure
C
A
K
48). After the
S
T
O
P
P
[AK4691]
2007/11