AK4691EG AKM [Asahi Kasei Microsystems], AK4691EG Datasheet - Page 66

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AK4691EG

Manufacturer Part Number
AK4691EG
Description
4ch ADC + 2ch DAC with MIC/HP/SPK-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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MS0672-E-00
Addr
01H
PMBP: BEEP Input Power Management
PMDAC: DAC Power Management
PMLO: Stereo Lineout Power Management
PMSPK: Speaker-Amp Power Management
PMHPL: Headphone-Amp Lch Power Management
PMHPR: Headphone-Amp Rch Power Management
HPMTN: Headphone-Amp Mute Control
Each block can be powered-down respectively by writing “0” to each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0” in the 00H and 01H addresses, PMPLL bit and MCKO bit is “0”, all blocks
are powered-down. The register values remain unchanged.
When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks
must always be present.
0: Power-down (default)
1: Power-up
0: Power-down (default)
1: Power-up
0: Power-down (default)
1: Power-up
0: Power-down (default)
1: Power-up
0: Power-down (default)
1: Power-up
0: Power-down (default)
1: Power-up
0: Mute (default)
1: Normal operation
Register Name
Power Management 2
Both PMDAC and PMBP bits should be set to “1” when DAC is powered-up for playback. After that, BEEPL,
BEEPH, BEEPS, MICL1, MICR1, or MICL2 bit is used to control each path when BEEP input is used.
Default
R/W
RD
D7
0
0
HPMTN
R/W
D6
0
PMHPR
- 66 -
R/W
D5
0
PMHPL
R/W
D4
0
PMSPK
R/W
D3
0
PMLO
R/W
D2
0
PMDAC
R/W
D1
0
[AK4691]
2007/11
PMBP
R/W
D0
0

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