AK4691EG AKM [Asahi Kasei Microsystems], AK4691EG Datasheet - Page 43

• Manufacturer Part Number: AK4691EG
• Description: 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

3. Example of ALC Operation
Table 33
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADC1=PMADC2 = PMDAC bits = “0”.
MS0672-E-00
Register Name
LMTH1-0
ZELMN
ZTM1-0
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
ALC
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, GSEL, RFST1-0, LFST bits
WR (LFST, RFST1-0, GSEL, LMTH1-0)
shows the examples of the ALC setting for MIC recording.
WR (ZELMN, RGAIN1-0, LMAT1-0)
Note : WR : Write
WR (ZTM1-0, WTM2-0)
Comment
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
Maximum gain at recovery operation
Gain of IVOL
Limiter ATT step
Recovery GAIN step
ALC enable
WR (IVL/R7-0)
ALC Operation
WR (ALC= “1”)
WR (REF7-0)
Manual Mode
larger data to ZTM1-0 bits
Figure 26. Registers set-up sequence at ALC operation
* The value of IVL/R should be
Table 33. Example of the ALC setting
the same or smaller than REF’s
- 43 -
Example:
Data
E1H
E1H
001
01
01
00
00
0
1
MIC Input Recording
Limiter = Zero crossing Enable
Recovery Cycle = 21.3ms@48kHz
Zero Crossing Timeout Period = 21.3ms@48kHz
Limiter and Recovery Step = 1
Fast Limiter/Recovery Speed = 4 step
Gain of IVOL = +30.0dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
LFST bit = “0”
ALC bit = “1”
fs=8kHz
(5) Addr=0EH & 10H, Data=E1H
−4.1dBFS
Operation
(1) Addr=0AH, Data=1BH
(3) Addr=0CH, Data=01H
(4) Addr=0DH, Data=E1H
(2) Addr=0BH, Data=00H
(6) Addr=12H, Data=04H
Enable
Enable
+30dB
+30dB
1 step
1 step
32ms
32ms
Data
E1H
E1H
011
01
11
00
00
0
1
fs=48kHz
−4.1dBFS
Operation
21.3ms
21.3ms
Enable
Enable
+30dB
+30dB
1 step
1 step
[AK4691]
2007/11