AK4691EG AKM [Asahi Kasei Microsystems], AK4691EG Datasheet - Page 23

• Manufacturer Part Number: AK4691EG
• Description: 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

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1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the LRCK and BICK pins change to “L” and irregular frequency clock is output from the MCKO pin at
MCKO bit is “1” before the PLL sets to lock state after PMPLL bit = “0”
changes to “L”
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, the BICK and LRCK pins do not output irregular frequency clocks but change to
“L” by setting PMPLL bit to “0”.
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL sets to lock state after PMPLL bit = “0”
“1”. Then, the clock selected by
data when the PLL is unlocked. For DAC, the output signal can be muted by writing “0” to DACL, DACH and DACS
bits.
MS0672-E-00
PLL State
After after PMPLL bit “0”
PLL Unlock (except above case)
PLL Lock
PLL Unlock State
(Table
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
After that PMPLL bit “0”
PLL Unlock
PLL Lock
7).
Table 9
“1”
MCKO bit = “0”
is output from the MCKO pin when PLL is locked. ADC and DAC output invalid
“L” Output
“L” Output
“L” Output
“1”
MCKO pin
- 23 -
MCKO bit = “0”
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
Table 9
Invalid
Invalid
MCKO pin
“1”. If MCKO bit is “0”, the MCKO pin
MCKO bit = “1”
“L” Output
Invalid
Invalid
Output
BICK pin
Table 10
Invalid
“L” Output
LRCK pin
1fs Output
Invalid
[AK4691]
2007/11