TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 108

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
JTAG Boundary-Scan Specification
Table 47. TAP Controller States in the Data Register Branch
Table 48. TAP Controller States in the Instruction Register Branch
108
TEST LOGIC RESET
RUN TEST/IDLE
CAPTURE-IR
CAPTURE-DR
EXIT(1/2)-IR
EXIT(1/2)-DR
UPDATE-IR
SELECT-IR
UPDATE-DR
SELECT-DR
PAUSE-IR
PAUSE-DR
SHIFT-IR
SHIFT-DR
Name
Name
This state is used for branching to the instruction register control.
The instruction code 0001 is loaded in the first stage of the instruction register
The instructions are clocked into the instruction register serially to the rising edge
This temporary state causes a branch to a subsequent state.
The input and output of instructions can be interrupted in this state.
The instruction is clocked into the second stage of the instruction register parallel
parallel to the rising edge of TCK in this state.
of TCK in the state. The TDO output driver is active.
to the falling edge of TCK in this state.
The BS logic is switched in such a way that normal operation of the ASIC is
adjusted. The IDCODE instruction is initialized by TEST LOGIC RESET. Irre-
spective of the initial state, the TAP controller has achieved TEST LOGIC
RESET after five control pulses at the latest when TMS = 1. The TAP controller
then remains in this state. This state is also achieved when TRST = 0.
Using the appropriate instructions, this state can activate circuit parts or initiate
a test. All of the registers remain in their present state if other instructions are
used.
This state is used for branching to the test data register control.
The test data is loaded in the test data register parallel to the rising edge of TCK
in this state.
The test data is clocked by the test data register serially to the rising edge of
TCK in the state. The TDO output driver is active.
This temporary state causes a branch to a subsequent state.
The input and output of test data can be interrupted in this state.
The test data is clocked into the second stage of the test data register parallel to
the falling edge of TCK in this state.
(continued)
Description
Description
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000