TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 111

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

Preliminary Data Sheet
October 2000
Microprocessor Interface
Overview
The TFRA08C13 device is equipped with a micropro-
cessor interface that can operate with most commer-
cially available microprocessors. The microprocessor
interface provides access to all the internal registers
through a 12-bit address bus and an 8-bit data bus.
Input MPMODE (pin AF9) is used to configure this
interface into one of two possible modes, as shown in
Table 51. The MPMODE setting selects the associated
set of control signals required to access a set of regis-
ters within the device.
The microprocessor interface can operate at speeds up
to 33 MHz in interrupt-driven or polled mode without
requiring any wait-states. For microprocessors operat-
ing at greater than 33 MHz, the RDY_DTACK output
(pin V26) may be used to introduce wait-states in the
read/write cycles.
In the interrupt-driven mode, one or more device
alarms will assert the INTERRUPT output (pin AD9)
once per alarm activation. After the microprocessor
identifies the source(s) of the alarm(s) (by reading the
Microprocessor Configuration Modes
Table 51 highlights the two microprocessor modes controlled by the MPMODE input (pin AF9)
Table 51 . Microprocessor Configuration Modes
* The DTACK signal is asynchronous to the MPCLK signal.
Lucent Technologies Inc.
Lucent Technologies Inc.
Mode 1
Mode 3
Mode
MPMODE
0
1
CS
CS
,
,
AS
ALE
,
,
DS
Generic Control, Data, and Output Pin Names
RD
, R/
,
WR
W
, A[11:0], D[7:0], INTERRUPT,
, A[11:0], D[7:0], INTERRUPT, RDY
global interrupt register) and reads the specific alarm
status registers, the INTERRUPT output will deassert.
In the polled mode, however, the microprocessor moni-
tors the various device alarm status by periodically
reading the alarm status registers within the
TFRA08C13 without the use of INTERRUPT. In both
interrupt and polled methods of alarm servicing, the
status registers within an identified block will clear on a
microprocessor read cycle only when the alarm condi-
tion within that block no longer exists; otherwise, the
alarm status register bit remains set.
The powerup default states for the line interface unit,
framer, and the HDLC blocks are discussed in their
respective sections. All read/write registers within
these blocks must be written by the microprocessor on
system start-up to guarantee proper device functional-
ity. Register addresses not defined in this data
sheet must not be written.
Details concerning the microprocessor interface con-
figuration modes, pinout definitions, clock specifica-
tions, register address map, I/O timing specifications,
and the I/O timing diagrams are described in the follow-
ing sections.
TFRA08C13 OCTAL T1/E1 Framer
DTACK
*
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