TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 6

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
Tables
6
Table 25. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT..................................................... 62
Table 26. Red Alarm or Loss of Frame Alignment Conditions ............................................................................... 68
Table 27. Remote Frame Alarm Conditions ........................................................................................................... 68
Table 28. Alarm Indication Signal Conditions ........................................................................................................ 69
Table 29. Sa6 Bit Coding Recognized by the Receive Framer. ............................................................................. 71
Table 30. Sa6 Bit Coding of NT1 Interface Events Recognized by the Receive Framer........................................ 71
Table 31. AUXP Synchronization and Clear Synchronization Process.................................................................. 72
Table 32. Event Counters Definition ...................................................................................................................... 73
Table 33. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a
Table 34. Register FRM_PR69 Test Patterns ........................................................................................................ 79
Table 35. Register FRM_PR70 Test Patterns ........................................................................................................ 80
Table 36. Automatic Enable Commands................................................................................................................ 82
Table 37. On-Demand Commands ........................................................................................................................ 83
Table 38. Receive ANSI Code ............................................................................................................................... 86
Table 39. Performance Report Message Structure................................................................................................ 86
Table 40. FDL Performance Report Message Field Definition............................................................................... 87
Table 41. Octet Contents and Definition ................................................................................................................ 87
Table 42. Receive Status of Frame Byte................................................................................................................ 88
Table 43. HDLC Frame Format.............................................................................................................................. 91
Table 44. Receiver Operation in Transparent Mode............................................................................................... 94
Table 45. Summary of the TFRA08C13’s Concentration Highway Interface Parameters ...................................... 99
Table 46. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0 .................................................... 104
Table 47. TAP Controller States in the Data Register Branch.............................................................................. 108
Table 48. TAP Controller States in the Instruction Register Branch..................................................................... 108
Table 49. TFRA08C13’s Boundary-Scan Instructions ......................................................................................... 109
Table 50. IDCODE Register................................................................................................................................. 110
Table 51. Microprocessor Configuration Modes .................................................................................................. 111
Table 52. Mode [1 and 3] Microprocessor Pin Definitions.................................................................................... 112
Table 53. Microprocessor Input Clock Specifications .......................................................................................... 112
Table 54. TFRA08C13 Register Address Map..................................................................................................... 113
Table 55. Microprocessor Interface I/O Timing Specifications ............................................................................. 114
Table 56. Status Register and Corresponding Interrupt Enable Register for Functional Blocks.......................... 118
Table 57. Asserted Value and Deasserted State for GREG4 Bit 4 and Bit 6 Logic Combinations ...................... 118
Table 58. Register Summary ............................................................................................................................... 119
Table 59. Global Register Set (0x000—0x009) ................................................................................................... 123
Table 60. Framer Block Interrupt Status Register (GREG0) (000)....................................................................... 123
Table 61. Framer Block Interrupt Enable Register (GREG1) (001)...................................................................... 124
Table 62. FDL Block Interrupt Status Register (GREG2) (002) ........................................................................... 124
Table 63. FDL Block Interrupt Enable Register (GREG3) (003) .......................................................................... 124
Table 64. Global Control Register (GREG4) (004) .............................................................................................. 125
Table 65. Device ID and Version Registers (GREG5—GREG7) (005—007) ...................................................... 125
Table 66. Global Control Register (GREG8) (008) .............................................................................................. 126
Table 67. Global PLLCK Control Register (GREG9) (009) .................................................................................. 127
Table 68. Framer Status and Control Blocks Address Range (Hexadecimal)...................................................... 127
Table 69. Interrupt Status Register (FRM_SR0) (Y00) ........................................................................................ 128
Table 70. Facility Alarm Condition Register (FRM_SR1) (Y01) ........................................................................... 129
Table 71. Remote End Alarm Register (FRM_SR2) (Y02) .................................................................................. 130
Table 72. Facility Errored Event Register-1 (FRM_SR3) (Y03) ........................................................................... 131
Function of Activating the Primary Loopback Modes .......................................................................................... 76
Table of Contents
(continued)
Preliminary Data Sheet
Lucent Technologies Inc.
October 2000
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