TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 174

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
FDL Parameter/Control Registers ((A00—A0E); (A20—A2E); (B00—B0E);
(B20—B2E) (C00—C0E); (C20—C2E); (D00—D0E); (D20—D2E))
Table 176. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (A0B; A2B; B0B; B2B; C0B; C2B;
* If an FDL receive FIFO overrun occurs, as indicated by register FDL_SR0 bit 5 (FROVERUN) = 1, the FDL must be reset to restore proper
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operation of the FIFO. Following an FDL receive FIFO overrun, data extracted prior to the required reset may be corrupted.
Bit
0
1
2
3
4
5
6
7
FROVERUN FDL Receiver Overrun. This bit is set to 1 when the receive FIFO has overrun its
FTUNDABT
D0B; D2B)
FTDONE
Symbol
FRANSI
FREOF
FRIDL
FTEM
FRF
Transmit Done. This status bit is set to 1 when transmission of the current FDL frame
has been completed, either after the last bit of the closing flag or after the last bit of an
abort sequence. In the transparent mode (FDL_PR9 bit 6 = 1), this status bit is set when
the transmit FIFO is completely empty. A hardware interrupt is generated only if the cor-
responding interrupt-enable bit (FDL_PR2 bit 0) is set. This status bit is cleared to 0 by a
read of this register.
Transmitter Empty. If this bit is set to 1, the FDL transmit FIFO is at or below the pro-
grammed depth. A hardware interrupt is generated only if the corresponding interrupt-
enable bit (FDL_PR2 bit 1) is set. If DINT (FDL_PR0 bit 0) is 0, this status bit is cleared
by a read of this register. If FDINT (FDL_PR0 bit 0) is set to 1, this bit actually represents
the dynamic transmit empty condition, and is cleared to 0 only when the transmit FIFO is
loaded above the programmed empty level.
FDL Transmit Underrun Abort. A 1 indicates that an abort was transmitted because of
a transmit FIFO underrun. A hardware interrupt is generated only if the corresponding
interrupt-enable bit (FDL_PR2 bit 2) is set. This status bit is cleared to 0 by a read of this
register. This bit must be cleared to 0 before further transmission of data is allowed. This
interrupt is not generated in the transparent mode.
FDL Receiver Full. This bit is set to 1 when the receive FIFO is at or above the pro-
grammed full level (FDL_PR6). A hardware interrupt is generated if the corresponding
interrupt-enable bit (FDL_PR2 bit 3) is set. If FDINT (FDL_PR0 bit 0) is 0, this status bit
is cleared to 0 by a read of this register. If FDINT (FDL_PR0 bit 0) is set to 1, then this bit
is cleared only when the receive FIFO is read (or emptied) below the programmed full
level*.
FDL Receive End of Frame. This bit is set to 1 when the receiver has finished receiving
a frame. It becomes 1 upon reception of the last bit of the closing flag of a frame or the
last bit of an abort sequence. A hardware interrupt is generated only if the corresponding
interrupt-enable bit (FDL_PR2 bit 4) is set. This status bit is cleared to 0 by a read of this
register. This interrupt is not generated in the transparent mode.
capacity. A hardware interrupt is generated only if the corresponding interrupt-enable bit
(FDL_PR2 bit 5) is set. This status bit is cleared to 0 by a read of this register*.
FDL Receiver Idle. This bit is set to 1 when the FDL receiver is idle (i.e., 15 or more
consecutive ones have been received). A hardware interrupt is generated only if the cor-
responding interrupt-enable bit (FDL_PR2 bit 6) is set. This status bit is cleared to 0 by a
read of this register. This interrupt is not generated in the transparent mode.
FDL Receive ANSI Bit Codes. This bit is set to 1 when the FDL receiver recognizes a
valid T1.403 ESF FDL bit code. The receive ANSI bit code is stored in register
FDL_SR3. An interrupt is generated only if the corresponding interrupt enable of register
FDL_PR6 bit 7 = 1. This status bit is cleared to 0 by a read this register.
Description
Preliminary Data Sheet
(continued)
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000