TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 92

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link
Flags
All flags have the bit pattern 01111110 and are used for
frame synchronization. The FDL HDLC block automati-
cally sends two flags between frames. If the chip-con-
figuration register FDL_PR0 bit 1 (FLAGS) is cleared to
0, the ones idle byte (11111111) is sent between
frames if no data is present in the FIFO. If FLAGS is set
to 1, the FDL HDLC block sends continuous flags when
the transmit FIFO is empty. The FDL HDLC does not
transmit consecutive frames with a shared flag; there-
fore, two successive flags will not share the intermedi-
ate 0.
An opening flag is generated at the beginning of a
frame (indicated by the presence of data in the transmit
FIFO and the transmitter enable register FDL_PR1 bit
3 = 1). Data is transmitted per the HDLC protocol until
a byte is read from the FIFO while register FDL_PR3
bit 7 (FTFC) set to 1. The FDL HDLC block follows this
last user data byte with the CRC sequence and a clos-
ing flag.
The receiver recognizes the 01111110 pattern as a
flag. Two successive flags may or may not share the
intermediate 0 bit and are identified as two flags (i.e.,
both 011111101111110 and 0111111001111110 are
recognized as flags by the FDL HDLC block). When the
second flag is identified, it is treated as the closing flag.
As mentioned above, a flag sequence in the user data
or CRC bits is prevented by zero-bit insertion and dele-
tion. The HDLC receiver recognizes a single flag
between frames as both a closing and opening flag.
Aborts
An abort is indicated by the bit pattern of the sequence
01111111. A frame can be aborted by writing a 1 to
register FDL_PR3 bit 6 (FTABT). This causes the last
byte written to the transmit FIFO to be replaced with
the abort sequence upon transmission. Once a byte is
tagged by a write to FTABT, it cannot be cleared by
subsequent writes to register FDL_PR3. FTABT has
higher priority than FDL transmit frame complete
(FTFC), but FTABT and FTFC should never be set to 1
simultaneously since this causes the transmitter to
enter an invalid state requiring a transmitter reset to
clear. A frame should not be aborted in the very first
byte following the opening flag. An easy way to avoid
this situation is to first write a dummy byte into the
queue and then write the abort command to the queue.
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*
(continued)
When receiving a frame, the receiver recognizes the
abort sequence whenever it receives a 0 followed by
seven consecutive ones. The receive FDL unit will
abort a frame whenever the receive framer detects a
loss of frame alignment. This results in the abort bit,
and possibly the bad byte count bit and/or bad CRC
bits, being set in the status of frame status byte (see
Table 42) which is appended to the receive data queue.
All subsequent bytes are ignored until a valid opening
flag is received.
Idles
In accordance with the HDLC protocol, the HDLC block
recognizes 15 or more contiguous received ones as
idle. When the HDLC block receives 15 contiguous
ones, the receiver idle bit register FDL_SR0 bit 6
(RIDL) is set.
For transmission, the ones idle byte is defined as the
binary pattern 11111111 (FF (hex)). If the FLAGS con-
trol bit in register FDL_PR0 bit 1 is 0, the ones idle byte
is sent as the time-fill byte between frames. A time-fill
byte is sent when the transmit FIFO is empty and the
transmitter has completed transmission of all previous
frames. Frames are sent back-to-back otherwise.
CRC-16
For given user data bits, 16 additional bits that consti-
tute an error-detecting code (CRC-16) are added by
the transmitter. As called for in the HDLC protocol, the
frame check sequence bits are transmitted most signifi-
cant bit first and are bit stuffed. The cyclic redundancy
check (or frame check sequence) is calculated as a
function of the transmitted bits by using the ITU-T stan-
dard polynomial:
The transmitter can be instructed to transmit a cor-
rupted CRC by setting register FDL_PR2 bit 7 (FTB-
CRC) to 1. As long as the FTBCRC bit is set, the CRC
is corrupted for each frame transmitted by logically flip-
ping the least significant bit of the transmitted CRC.
The receiver performs the same calculation on the
received bits after destuffing and compares the results
to the received CRC-16 bits. An error indication occurs
if, and only if, there is a mismatch.
* Regardless of the time-fill byte used, there always is an opening
and closing flag with each frame. Back-to-back frames are
separated by two flags.
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Preliminary Data Sheet
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+ x
Lucent Technologies Inc.
Lucent Technologies Inc.
5
+ 1
October 2000