TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 115

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TFRA08C13-DB

Manufacturer Part Number
TFRA08C13-DB
Description
TFRA08C13 OCTAL T1/E1 Framer
Manufacturer
AGERE [Agere Systems]
Datasheet
Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Microprocessor Interface
Table 55. Microprocessor Interface I/O Timing Specifications (continued)
Note: The read and write timing diagrams for all four microprocessor interface modes are shown in Figure 46—Figure 49.
Symbol Configuration
t31
t32
t33
t34
t35
t36
t37
t38
t39
t40
t41
t42
t43
t44
t45
t46
t47
t48
t49
t50
t51
t52
t53
t54
t55
Mode 3
ALE Asserted Width
Address Valid to ALE Deasserted
ALE Deasserted to Address Invalid
CS Asserted to RD Asserted
Address Valid and ALE Asserted to RD Asserted
CS Asserted to RDY Low Impedance
Rising Edge MPCK to RDY Asserted
RD Asserted to AD Low Impedance
RD Asserted to Data Valid
RD Deasserted to CS Deasserted
RD Deasserted to RDY Deasserted
CS Deasserted to RDY High Impedance
RD Deasserted to Data Invalid (High Impedance)
CS Asserted to WR Asserted
Address Valid and ALE Asserted to WR Asserted
Data Valid to WR Asserted
WR Deasserted to CS Deasserted
WR Deasserted to RDY Deasserted
WR Deasserted to Data Invalid
RD Asserted Width
WR Asserted Width
(continued)
Parameter
TFRA08C13 OCTAL T1/E1 Framer
Setup
(Min)
(ns)
10
10
10
5
5
6
(Min)
Hold
(ns)
10
10
10
40
50
5
5
7
Delay
(Max)
(ns)
12
15
19
40
15
10
15
115

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