TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 62

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
Signaling Access
Table 23 illustrates the ASM time-slot format for valid channels.
Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames
* X indicates bits that are undefined by the framer.
† The identical sense of the received system P bit in the transmitted signaling data is echoed back to the system in the received
The DS1 framing formats require rate adaptation from the line-interface 1.544 Mbits/s bit stream to the system-
interface 4.096 Mbits/s bit stream. The rate adaptation results in the need for stuffed time slots on the system inter-
face. Table 24 illustrates the ASM format for T1 stuffed channels used by the TFRA08C13. The stuffed data byte
contains the programmable idle code in register FRM_PR23 (default = 7F (hex)), while the signaling byte is
ignored.
Table 24. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels
* X indicates bits which are undefined by the framer.
CEPT: Time Slot 16 Signaling
Microprocessor Control Registers
To enable signaling, register FRM_PR44 bit 0 must be set to 0 (default).
The information written into transmit signaling control registers FRM_TSR0—FRM_TSR31 define the state of the
ABCD bits of time slot 16 transmitted to the line.
The received signaling data from time slot 16 is stored in receive signaling registers FRM_RSR0—FRM_RSR31.
Associated Signaling Mode
Signaling information in the associated signaling mode (ASM), register FRM_PR44 bit 2 = 1, is allocated an 8-bit
system time slot in conjunction with the data information for a particular channel. The default system data rate in
the ASM mode is 4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its associ-
ated 8-bit signaling time slot. The format of the signaling byte is identical to the signaling registers.
Table 25 illustrates the ASM time-slot format for valid CEPT E1 time slots
Table 25. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT
* In the CEPT formats, these bits are undefined.
† The P bit is the parity-sense bit calculated over the 8 data bits, the ABCD (and E) bits, and the P bit. The identical sense of the received
62
signaling information.
system P bit in the transmitted signaling data is echoed back to the system in the received signaling information.
1
0
1
2
1
2
3
1
3
PAYLOAD DATA
PAYLOAD DATA
PAYLOAD DATA
4
1
4
(continued)
5
1
5
6
1
6
CEPT ASM CHI Time Slot
DS1: ASM CHI Time Slot
7
1
7
ASM CHI Time Slot
8
1
8
A
X
A
B
X
B
SIGNALING INFORMATION*
SIGNALING INFORMATION*
SIGNALING INFORMATION
C
C
X
D
X
D
Preliminary Data Sheet
X
X
E
Lucent Technologies Inc.
Lucent Technologies Inc.
X
F
X
*
October 2000
X
G
X
*
P
P
X
†
†